Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2021, n. 3, p. 390–417, 2021. DOI: 10.46586/tches.v2021.i3.390-417. Disponível em: https://bmt.ub.rub.de/index.php/TCHES/article/view/8979.. Acesso em: 20 nov. 2024.