Automated Generation of Fault-Resistant Circuits. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2024, n. 3, p. 136–173, 2024. DOI: 10.46586/tches.v2024.i3.136-173. Disponível em: https://bmt.ub.rub.de/index.php/TCHES/article/view/11672.. Acesso em: 20 nov. 2024.